Issues

Other Journals Published by Timeline Publication Pvt. Ltd.

  • IJECCE
    IJECCE
  • IJEIR
    IJEIR
  • IJAIR
    IJAIR
  • IJAIM
    IJAIM
  • IJRAS
    IJRAS
  • IJISM
    IJISM
  • IJIRES
    IJIRES
  • IJASM
    IJASM
  • IJRIES
    IJRIES

Latest News

  • Submissions open

    "Submissions Open For Volume 11,Issue 5,Sept.-Oct., 2020"

  • Submissions open

    "Submissions Open For Volume 11,Issue 5,Sept.-Oct., 2020"

  • Successfully Published

    "Volume 11,Issue 4,July - Aug., 2020"

  • Send your paper at E-mail:

    submit2ijecce@yahoo.in , submit@ijecce.org

Implementation of 64-Bit Approximate Multiplier for Accurate and High-Level Processing

Ragini Singh; Prof. Sandip Nemade
Approximate computing has received significant attention as a promising strategy to enhance performance of multiplication. Various arithmetic operations such as multiplication addition, subtraction are important part of digital circuit to speed up the computation speed of processor. This paper presents 64 bit approximate multiplier for high speed and low delay for advance digital signal processing. Previous it is designed for 16 bit and 32 bit for various applications. Research work is focus on hardware-level approximation by introducing the partial product perforation technique and dadda multiplier for designing approximate multiplication circuits. Xilinx 14.7 is used to implementation with verilog programming language.
Select Volume / Issues:
Year:
2020
Type of Publication:
Article
Keywords:
Approximate; Dadda; Multiplier; Verilog; Speed
Journal:
IJECCE
Volume:
11
Number:
1
Pages:
1-7
Month:
January
ISSN:
2249-071X
Hits: 187

Indexed By:

  • 1.gif
  • 01.png
  • 1.png
  • 2.jpg
  • 2.png
  • 3.jpg
  • 3.png
  • 4.jpg
  • 4.png
  • 5.png
  • 6.jpg
  • 6.png
  • 7.jpg
  • 7.png
  • 8.jpg
  • 8.png
  • 9.jpeg
  • 9.jpg
  • 10.jpg
  • 10.png
  • 11.jpg
  • 11.png
  • 12.jpg
  • 12.png
  • 13.png
  • 14.jpg
  • 14.png
  • 15.jpg
  • 16.png
  • 17.jpg
  • 17.png
  • 19.png
  • copernicus.jpg
  • EuroPub-1.png