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Design and Implementation of Tied Output Dynamic Dual Clocked Comparator

Priya Patne; Sandip Nemade
Present day technology has completely shifted towards the digital paradigm. However, most of the practical real life signals and data happen to be analog in nature. Hence, the natural need for analog to digital conversion arises. However, how accurate the analog to digital conversion process would be depends on the effectiveness of the comparator circuit of the analog to digital converter circuit. The comparator performs the task of comparing two signals in general. There are several metrics which govern the efficacy of the comparator circuit which are the sampling frequency or speed, power consumption, worst case delay, supply voltage and size. Its always envisaged to design the comparator in such a way that it is compact, fast yet consumes low power. In the proposed work, a dynamic double-clocked comparator circuit is designed and evaluated In terms of the standard performance metrics. It has been shown that the proposed comparator circuit achieves lesser power consumption, size and higher clock frequency compared to conventional dual clocked comparators.
Select Volume / Issues:
Year:
2019
Type of Publication:
Article
Keywords:
Analog to Digital Converter ADC; Comparator; Double Clocked Comparator; Sampling Frequency; Power Consumption; Worst Case Delay; Technology Size
Journal:
IJECCE
Volume:
10
Number:
5
Pages:
232-242
Month:
September
ISSN:
2249-071X
Hits: 255

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