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Low Power and Area Efficient Reverse Converter Design via Parallel-Prefix Adders-A Review

Akanksha Gautam; Sandeep Nemade
The design of reverse convertor using parallel prefix adder based mostly multiplier for residue numeration system is projected. Today the parallel prefix adders aren't used although it provides vital delay reduction and high speed operation due to higher power consumption. The novel specific hybrid parallel prefix adder elements that compensate the delay and power consumption within the existing system are applied to style the reverse convertor. Totally different parallel adder structures are analyzed among that the brent Kung prefix network is used for the parallel prefix addition due to the minimum diffuse. Within the projected system the high speed parallel prefix adder styled for modulo (4n+1) addition for n=5 and thereby planning the multiplier by using the shifting operation within the same design.
Select Volume / Issues:
Year:
2017
Type of Publication:
Article
Keywords:
Parallel prefix Adder; Residue Number System; Reverse Converter
Journal:
IJECCE
Volume:
8
Number:
4
Pages:
220-222
Month:
July
ISSN:
2249-071X
Hits: 36

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